1. Field of the Invention
This invention relates to a computer system and, more particularly, to a microcontroller which provides a programmably sized data bus forwarded to system memory and input/output space. The variably sized data bus allows a more flexible computer system application, and is compatible to either a multiplexed data/address bus or a stand-alone data bus.
2. Description of Related Art
A typical computer system includes, at a minimum, an execution unit, memory, and at least one peripheral device operably connected to the execution unit and/or the memory. Signals within an address bus, comprising a series of address lines forwarded from the execution unit, are decoded to access data within the memory or the input/output space occupied by a peripheral. Earlier designs mandated the address lines be time multiplexed with data lines such that the corresponding bus comprised both address and data information. Advances in access speed to the peripheral has led to direct memory access ("DMA"). DMA occurs whenever the memory is accessed by the peripheral devices without involving the execution unit.
The data being addressed resides within an address space possibly bifurcated into numerous elements (blocks or chips). The task of address decoding is therefore not only to select a defined space, but also to select the bifurcated element among the other elements. For example, the memory being selected can be from different memory types and of different memory sizes. For example, memory address space can comprise one or more read only memory (ROM) elements in conjunction with one or more randomly accessibly, read/write memory (RAM) elements. The address forwarded across the address bus or address/data bus is decoded by the ROM or the RAM, depending upon which is selected.
In addition to memory address space, the address bus can also address input/output address space. Thus, a peripheral can be called upon depending upon where that peripheral resides within the addressed input/output address space. Many modem computer system designs employ a microcontroller to interface with the various memory and input/output elements. A popular microcontroller is the Am186 design, which is produced and marketed by Advanced Micro Devices, Inc. The Am186 reserves 20 dedicated address lines and 16 address/data lines for accessing PROM, SRAM and DRAM within the memory address space. The address lines or address/data lines can also access various input/output ports within an input/output address space. The various memory elements and peripheral devices are selected based on the status of chip select signals forwarded thereto. Am186 microcontroller dispatches an upper chip select (UCS), a lower chip select (LCS) and, depending upon the additional memory elements needed, allows for additional chip select MCSO-3, etc.
The upper, lower and middle chip selects can address up to 1 Mbytes memory address space, with the upper address space being reserved for non-volatile data preferably needed to boot the computer system during a power-on reset. In addition to the 1 Mbytes memory address space, an input/output address space is also provided. The input/output space is, according to the Am186 embodiment, 64 Kbytes addressable by the address/data bus or dedicated address bus. The input/output space preferably consists of 32K 16-bit ports.
Memory within the Am186 is organized in sets of elements. Each element is a linear continuous sequence of 64 K (i.e., 2.sup.16) 8-bit bytes. While the logical address accessible from the 16-bit address or address/data bus is only 64 Kbytes, it is recognized that the memory is addressed using a two-component address consisting of a 16-bit segment value and a 16-bit offset. The two-component addressing system allows a physical address of 2.sup.20, or 1 Mbyte. All instructions used by the Am186 which address operands in memory must specify the segment value and a 16-bit offset value. Description of the various instructions and the two-component addressing scheme is well known and recognized in the 186/188 art.
Conventional bus width needed to access the memory address space and/or the input/output space is defined as a 16-bit bus. Thus, regardless of the amount of memory or input/output port size needed, conventional designs are unfortunately fixed to a specific bus width. It would be desirable to re-design the microcontroller interface for more flexibility. Specifically, an improved microcontroller is needed which can vary the data bus width depending upon the size of memory and/or input/output space. In many applications, the memory can be made quite small or the number of peripherals reduced to match that application. In instances where lower performance is suitable, it would be desirable to lessen the size of the data bus to match the smaller memory and input/output addressing space. A need therefore exists for a microcontroller which can programmably change the data bus size to accommodate large and small address spaces and, correspondingly, high performance and low performance applications.